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[VHDL-FPGA-Verilog] ddr_code

Description: 基于FPGA的DDR SDRAM控制器的VHDL硬件描述语言-FPGA-based DDR SDRAM controller VHDL hardware description language
Platform: | Size: 11264 | Author: 阳阳 | Hits:

[Software Engineering] ddr_sdr_V1_1

Description: its the vhdl stuff for ddr sdram controller nice one easily understandable-its the vhdl stuff for ddr sdram controller nice one easily understandable
Platform: | Size: 37888 | Author: james | Hits:

[VHDL-FPGA-Verilog] Altera_DDR_controller_core

Description: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Platform: | Size: 752640 | Author: 沈志 | Hits:

[VHDL-FPGA-Verilog] DDRsdram2

Description: 一个DDR2 的控制器源码，它是由LATTICE的编译器生成。-A DDR2 controller source code, which is generated by the compiler LATTICE.
Platform: | Size: 969728 | Author: 召唤 | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM

Description: 本应用指南描述了在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。该实现运用了直接时钟控制技术来实现数据采集，并采用自动校准电路来调整数据线上的延迟。-This application note describes a Virtex ™ -4 XC4VLX25 FF668-10C to implement the DDR SDRAM device controller. The clock control to achieve use of technology to achieve direct data acquisition, and automatic calibration circuit to adjust the data in line delay.
Platform: | Size: 54272 | Author: syf | Hits:

[VHDL-FPGA-Verilog] mictor20110113

Description: ddr控制参考代码,串口通信可以基于此进行二次开发,fpga参考设计，对ddr设计开发有一定的帮助-ddr controller ref code
Platform: | Size: 986112 | Author: wangqijun | Hits:

[VHDL-FPGA-Verilog] model

Description: 用vhdl写的 ddr sdram 控制器,数据位可以修改。在quartus2下仿真通过-With written ddr sdram controller vhdl
Platform: | Size: 7168 | Author: momowang | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM

Description: DDR SDRAM的设计，包括DDR SDRAM控制器，以及Modelsim仿真-The design of DDR SDRAM, DDR SDRAM controller, and Modelsim simulation
Platform: | Size: 897024 | Author: xinghe | Hits:

[Windows Develop] DDR-SDRAM

Description: ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
Platform: | Size: 903168 | Author: 何海山 | Hits:

[Windows Develop] treff-ddr-sdrh

Description: 本程序源码是DDR SDRAM控制器的VHDL程序源源码，由ALTERA 提供 -The program source code is DDR SDRAM controller VHDL source source code provided by ALTERA
Platform: | Size: 439296 | Author: wyq52103 | Hits:

[VHDL-FPGA-Verilog] ddr_verilog

Description: DDR控制器的VERILOG代码；状态机；读写；刷新等操作-ddr controller,verilog
Platform: | Size: 677888 | Author: 雷恒伟 | Hits:

[VHDL-FPGA-Verilog] bl-8-gai-add24

Description: 迸发长度为8的DDR控制器，实现数据的读写，使用赛灵思的V2板子就行验证-Burst length 8 DDR controller, read and write data, and on line verification using Xilinx V2 board
Platform: | Size: 8250368 | Author: zhangjiefei | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM-controller-verilog-code

Description: DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM controller verilog code and documentation
Platform: | Size: 488448 | Author: 一样 | Hits:

[VHDL-FPGA-Verilog] ddr-sdram-control

Description: ddr sdram控制器的设计与验证，提供了一种极为可靠且简易的控制器设计方案。-DDR SDRAM controller design and verification, providing an extremely reliable and simple controller design.
Platform: | Size: 769024 | Author: 毛洋 | Hits:

[VHDL-FPGA-Verilog] ddr_kongzhiqi

Description: fpga上用verilog HDL实现的ddr控制器，简单易懂，适合新手参考-FPGA on the use the verilog HDL implementation of the DDR controller, easy to understand, suitable for novice reference
Platform: | Size: 18432 | Author: fan | Hits:

[Other] DDR-SDRAM

Description: DDR SDRAM控制器的FPGA实现-DDR SDRAM Controller with FPGA
Platform: | Size: 249856 | Author: pzf | Hits:

[VHDL-FPGA-Verilog] DDRController

Description: DDR3控制器，用于FPGA内部对DDR进行操作，利用Avlone总线进行对接-DDR controller
Platform: | Size: 7168 | Author: wang | Hits:

[VHDL-FPGA-Verilog] xilinx_ddr_verilog

Description: xilinx赛灵思的DDR控制器源码（包括仿真与说明文档），DDR为mt46v4m16。-Xilinx DDR controller source code (including simulation and documentation), DDR is mt46v4m16.
Platform: | Size: 131072 | Author: 刘佳庆 | Hits:

[VHDL-FPGA-Verilog] altera_ddr_verilog

Description: altera的DDR控制器源码（包括仿真与说明文档），DDR为mt46v4m16，Verilog-The DDR controller source of altera (including simulation and documentation), DDR is mt46v4m16, Verilog
Platform: | Size: 753664 | Author: 刘佳庆 | Hits:

[VHDL-FPGA-Verilog] lattice_ddr_verilog-for-orca4

Description: 莱迪思的DDR控制器源码（包括仿真与说明文档），DDR为MT46V16M8，Verilog-The DDR controller source of Lattice (including simulation and documentation), DDR is MT46V16M8, Verilog
Platform: | Size: 615424 | Author: 刘佳庆 | Hits:
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